UI=ST, SRI=ST, UEI=ST, URI=ST, NAKI=ENDPCLEAR, PCI=ST, SLI=ST
USB status (device mode)
| UI | USB interrupt 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. |
| UEI | USB error interrupt 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6). |
| PCI | Port change detect. 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively. |
| RESERVED | Not used in Device mode. |
| RESERVED | Reserved. |
| RESERVED | Not used in Device mode. |
| URI | USB reset received 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. |
| SRI | SOF received 0 (ST): This bit is cleared by software writing a one to it. 1 (CLEAR): When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125 ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. |
| SLI | DCSuspend 0 (ST): The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it. 1 (CLEAR): When a device controller enters a suspend state from an active state, this bit will be set to a one. |
| RESERVED | Reserved. Software should only write 0 to reserved bits. |
| RESERVED | Not used in Device mode. |
| RESERVED | Not used in Device mode. |
| RESERVED | Not used in Device mode. |
| RESERVED | Not used in Device mode. |
| NAKI | NAK interrupt bit 0 (ENDPCLEAR): This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. 1 (SET): It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. |
| RESERVED | Reserved. Software should only write 0 to reserved bits. |
| RESERVED | Not used in Device mode. |
| RESERVED | Not used in Device mode. |
| RESERVED | Reserved. Software should only write 0 to reserved bits. |